High-Level Block Diagram
A simplified, logical overview of the core datapath and control unit routing.
%%{init: {'theme': 'base', 'themeVariables': { 'primaryColor': '#1e293b', 'primaryTextColor':
'#e2e8f0', 'primaryBorderColor': '#3b82f6', 'lineColor': '#64748b', 'tertiaryColor': '#0f172a' }}}%%
graph LR
PC([Program Counter]) --> IMEM[(Instruction Memory)]
IMEM --> IR>Instruction Register]
IR --> CTRL((Control Unit))
IR --> REG[[Register File]]
REG --> ALU{{ALU}}
ALU --> DMEM[(Data Memory)]
DMEM --> REG
CTRL -.-> IMEM
CTRL -.-> IR
CTRL -.-> REG
CTRL -.-> ALU
CTRL -.-> DMEM
CTRL -.-> PC
classDef default fill:#1e293b,stroke:#3b82f6,stroke-width:2px,color:#e2e8f0;
classDef control fill:#1e1b4b,stroke:#8b5cf6,stroke-width:2px,stroke-dasharray: 5 5;
class CTRL control;
Architecture Specifications
Operational
Architecture Type
32-Bit Single-Stage
Register File
32x32-bit Registers
Instruction Memory
4KB (1024 Words)
Data Memory
4KB (1024 Words)
Atomic Operations
LL / SC Support
Byte Enables
Load/Store Partial
Instruction Set
0 Instructions
The CPU supports a comprehensive subset of the MIPS ISA, including Arithmetic, Logical, Memory, and Branching instructions.